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HUF76609D3, HUF76609D3S
Data Sheet October 1999 File Number 4688.2
10A, 100V, 0.165 Ohm, N-Channel, Logic Level UltraFET Power MOSFET Packaging
JEDEC TO-251AA
DRAIN (FLANGE)
Features
JEDEC TO-252AA
DRAIN (FLANGE)
SOURCE DRAIN GATE
* Ultra Low On-Resistance - rDS(ON) = 0.160, VGS = 10V - rDS(ON) = 0.165, VGS = 5V * Simulation Models - Temperature Compensated PSPICE(R) and SABER(c) Electrical Models - Spice and SABER(c) Thermal Impedance Models - www.Intersil.com * Peak Current vs Pulse Width Curve * UIS Rating Curve
GATE SOURCE
HUF76609D3
HUF76609D3S
Symbol
D
* Switching Time vs RGS Curves
Ordering Information
PART NUMBER PACKAGE TO-251AA TO-252AA BRAND 76609D 76609D HUF76609D3 HUF76609D3S
G
S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the variant in tape and reel, e.g., HUF76609D3ST.
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified HUF76609D3, HUF76609D3S UNITS V V V A A A A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TC= 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TC= 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTE:
100 100 16 10 10 7 7 Figure 4 Figures 6, 17, 18 49 0.327 -55 to 175 300 260
W W/oC
oC oC oC
1. TJ = 25oC to 150oC. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures. UltraFETTM is a trademark of Intersil Corporation. PSPICE(R) is a registered trademark of MicroSim Corporation. SABER(c) is a Copyright of Analogy Inc.http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HUF76609D3, HUF76609D3S
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVDSS IDSS IGSS VGS(TH) rDS(ON) ID = 250A, VGS = 0V (Figure 12) ID = 250A, VGS = 0V, TC = -40oC (Figure 12) Zero Gate Voltage Drain Current VDS = 95V, VGS = 0V VDS = 90V, VGS = 0V, TC = 150oC Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS = VDS, ID = 250A (Figure 11) ID = 10A, VGS = 10V (Figures 9, 10) ID = 7A, VGS = 5V (Figure 9) ID = 7A, VGS = 4.5V (Figure 9) THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-251 and TO-252 3.06 100
oC/W oC/W
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
100 90 -
-
1 250 100 3 0.160 0.165 0.168
V V A A nA
VGS = 16V
1 -
0.130 0.135 0.140
V
SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) tr td(OFF) tf tOFF tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 13) VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 50V, ID = 7A, Ig(REF) = 1.0mA (Figures 14, 19, 20) VDD = 50V, ID = 10A VGS = 10V, RGS = 24 (Figures 16, 21, 22) VDD = 50V, ID = 7A VGS = 4.5V, RGS = 20 (Figures 15, 21, 22) 10 41 30 28 77 87 ns ns ns ns ns ns
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance 425 75 22 pF pF pF 13 7.3 0.5 1.4 3.4 16 8.8 0.6 nC nC nC nC nC 6 18 55 39 36 141 ns ns ns ns ns ns
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage SYMBOL VSD trr QRR ISD = 7A ISD = 4A Reverse Recovery Time Reverse Recovered Charge ISD = 7A, dISD/dt = 100A/s ISD = 7A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 1.0 92 273 UNITS V V ns nC
2
HUF76609D3, HUF76609D3S Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 9 VGS = 4.5V 6 VGS = 10V 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC) 12
3
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
2 1 THERMAL IMPEDANCE ZJC, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 SINGLE PULSE t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
0.01 10-5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
IDM, PEAK CURRENT (A)
100
TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150
VGS = 5V 10 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
5
10-5
FIGURE 4. PEAK CURRENT CAPABILITY
3
HUF76609D3, HUF76609D3S Typical Performance Curves
100 IAS, AVALANCHE CURRENT (A)
(Continued)
100 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] STARTING TJ = 25oC
ID, DRAIN CURRENT (A)
10
100s
10
1
OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) SINGLE PULSE TJ = MAX RATED TC = 25oC 1 10 100
1ms 10ms
STARTING TJ = 150oC
0.1
1 300 0.001 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 15
20
VGS = 10V VGS = 5V VGS = 3.5V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
15
VGS = 4V
10
10 VGS = 3V 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 1 2 3 4 5
5 TJ = 25oC 0 1.5 2.0
TJ = 175oC TJ = -55oC 2.5 3.0 3.5 4.0
0
VGS, GATE TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
200 ID = 10A rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m) 180 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC
3.0 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 2.5 VGS = 10V, ID = 10A 2.0
160 ID = 4A 140 ID = 7A
1.5
120
1.0
100 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V)
0.5 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
4
HUF76609D3, HUF76609D3S Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250A NORMALIZED GATE THRESHOLD VOLTAGE 1.0
(Continued)
1.2 ID = 250A
1.1
0.8
1.0
0.6
0.4 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
0.9 -80 -40 0 40 80 120 160 200 TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
2000 1000 C, CAPACITANCE (pF) CISS = CGS + CGD COSS CDS + CGD 100
10 VDD = 50V 8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 10A ID = 7A ID = 4A 0 3 6 9 12 15
CRSS = CGD 10 VGS = 0V, f = 1MHz 5 0.1 1 10 100 VDS , DRAIN TO SOURCE VOLTAGE (V)
2
0
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
80 VGS = 4.5V, VDD = 50V, ID = 7A tr SWITCHING TIME (ns) 60 td(OFF) 40 tf SWITCHING TIME (ns)
120 VGS = 10V, VDD = 50V, ID = 10A 90 td(OFF)
60 tf 30 tr td(ON) 0
20 td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
5
HUF76609D3, HUF76609D3S Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
VDD DUT 0
10% 90%
10%
RGS VGS VGS 0 10% 50% PULSE WIDTH 50%
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
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HUF76609D3, HUF76609D3S PSPICE Electrical Model
.SUBCKT HUF76609D3 2 1 3 ;
CA 12 8 7.5e-10 CB 15 14 7.6e-10 CIN 6 8 4.03e-10
DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18
rev 23 August 1999
LDRAIN 10 RSLC1 51 ESLC 50 DRAIN 2
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 116.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 3.7e-9 LSOURCE 3 7 3.4e-9 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
S1A LGATE GATE 1 RLGATE
RSLC2
5 51
ESG + EVTEMP RGATE + 18 22 9 20 6 8 EVTHRES + 19 8 6
MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S2A RBREAK 17 18 RVTEMP CB + 6 8 EDS 5 8 14 IT 19 7 SOURCE 3
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 9.4e-2 RGATE 9 20 3.3 RLDRAIN 2 5 10 RLGATE 1 9 37 RLSOURCE 3 7 34 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.3e-2 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
12 S1B CA
13 8 13
14 13 S2B +
15
EGS
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*17.3),3.5))} .MODEL DBODYMOD D (IS = 1.2e-12 RS = 1.2e-2 TRS1 = 1.2e-3 TRS2 = 1.03e-6 CJO = 6.7e-10 TT = 6.9e-8 M = 0.77) .MODEL DBREAKMOD D (RS = 9.9e-1 TRS1 = 1e-3 TRS2 = -2e-5) .MODEL DPLCAPMOD D (CJO = 4.3e-10 IS = 1e-30 M = 0.9 N = 10) .MODEL MMEDMOD NMOS (VTO = 1.88 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.3) .MODEL MSTROMOD NMOS (VTO = 2.13 KP = 12.4 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.59 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 33 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -5e-7) .MODEL RDRAINMOD RES (TC1 = 8.1e-3 TC2 = 2.4e-5) .MODEL RSLCMOD RES (TC1 = 3e-3 TC2 = 2e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -1.5e-3 TC2 = -4.3e-6) .MODEL RVTEMPMOD RES (TC1 = -1.6e-3 TC2 = 1.5e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.5 VOFF= -2.5) VON = -2.5 VOFF= -4.5) VON = -0.3 VOFF= 0.2) VON = 0.2 VOFF= -0.3)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
7
+
-
RDRAIN 21 16
DBODY
MWEAK MMED
VBAT +
8 22 RVTHRES
HUF76609D3, HUF76609D3S SABER Electrical Model
REV 23 August 1999 template huf76609d3 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is = 1.2e-12, n = 1.05, cjo = 6.7e-10, tt = 6.9e-8, m = 0.77) d..model dbreakmod = () d..model dplcapmod = (cjo = 4.3e-10, is = 1e-30, n = 10, m = 0.9 ) m..model mmedmod = (type=_n, vto = 1.88, kp = 5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.13, kp = 12.4, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 1.59, kp = 0.12, is = 1e-30, tox = 1) DPLCAP sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -2.5, voff = -4.5) 10 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3) c.ca n12 n8 = 7.5e-10 c.cb n15 n14 = 7.6e-10 c.cin n6 n8 = 4.03e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 3.7e-9 l.lsource n3 n7 = 3.4e-9
GATE 1 RLGATE CIN LGATE RSLC2 ISCL
LDRAIN 5 RLDRAIN RDBREAK 72 DBREAK 11 MWEAK MMED MSTRO 8 EBREAK + 17 18 71 RDBODY DRAIN 2 RSLC1 51
ESG + EVTEMP RGATE + 18 22 9 20 6 6 8 EVTHRES + 19 8
50 RDRAIN 21 16
DBODY
-
LSOURCE 7 RLSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
S1A S2A 14 13 S2B 13 + EGS 6 8 EDS CB + 5 8 14 15
SOURCE 3
RSOURCE 12 RBREAK 17 18 RVTEMP 19 IT
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7 res.rdbody n71 n5 = 1.2e-2, tc1 = 1.2e-3, tc2 = 1.03e-6 res.rdbreak n72 n5 = 9.9e-1, tc1 = 1e-3, tc2 = -2e-5 res.rdrain n50 n16 = 9.4e-2, tc1 = 8.1e-3, tc2 = 2.4e-5 res.rgate n9 n20 = 3.3 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 37 res.rlsource n3 n7 = 34 res.rslc1 n5 n51 = 1e-6, tc1 = 3e-3, tc2 = 2e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.3e-2, tc1 = 1e-3, tc2 = 1e-6 res.rvtemp n18 n19 = 1, tc1 = -1.6e-3, tc2 = 1.5e-6 res.rvthres n22 n8 = 1, tc1 = -1.5e-3, tc2 = -4.3e-6 spe.ebreak n11 n7 n17 n18 = 116.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
13 8 S1B
CA
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/17.3))** 3.5)) } }
8
HUF76609D3, HUF76609D3S SPICE Thermal Model
REV 23 August 1999 T76609d3 CTHERM1 th 6 9.50e-4 CTHERM2 6 5 2.40e-3 CTHERM3 5 4 3.90e-3 CTHERM4 4 3 4.10e-3 CTHERM5 3 2 5.60e-3 CTHERM6 2 tl 4.00e-2 RTHERM1 th 6 2.00e-2 RTHERM2 6 5 1.10e-1 RTHERM3 5 4 2.75e-1 RTHERM4 4 3 5.53e-1 RTHERM5 3 2 7.25e-1 RTHERM6 2 tl 7.56e-1
th JUNCTION
RTHERM1
CTHERM1
6
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model t76609d3 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 9.50e-4 ctherm.ctherm2 6 5 = 2.40e-3 ctherm.ctherm3 5 4 = 3.90e-3 ctherm.ctherm4 4 3 = 4.10e-3 ctherm.ctherm5 3 2 = 5.60e-3 ctherm.ctherm6 2 tl = 4.00e-2 rtherm.rtherm1 th 6 = 2.00e-2 rtherm.rtherm2 6 5 = 1.10e-1 rtherm.rtherm3 5 4 = 2.75e-1 rtherm.rtherm4 4 3 = 5.53e-1 rtherm.rtherm5 3 2 = 7.25e-1 rtherm.rtherm6 2 tl = 7.56e-1 }
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
CASE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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9

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